Question on cache memory


Consider 4-way set-associative cache memory has the following properties:
---->Data words are 32 bits each
---->A cache block will contain 2048 bits of data
---->The address supplied from the CPU is 32 bits long
---->There are 2048 blocks in the cache
---->Addresses are to the word
Number of bits in tag?


option A.
There are still 6 bits in the offset; data is word addressed
Number of bits in index…
– We now need one less bit of index because we address to the set
→ 2^11 blocks / 2^2 blocks/set = 2^9 sets
→ (9 bits of index needed)
Number of bits in tag…
→ 32 – 6 – 9 = 17 bits.