Query on cache memory


#1

suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of the L1 cache is 1 clock cycle. what is average memory access time?


#2

1st we need to calculate the miss rate for each level of cache
so, for L1 cache the miss rate is 40/100 ie 4% and for L2 cache the miss ate is 20/40 ie 50% (this is for the local L2 cache). For the global L2 cache, it is 20/1000 ie 2%.
now, average memory access time = hit time L1 + miss rate L1 * (hit time L2 + miss rate L2 + miss penalty L2)
= 1 + 4% * (10 + 50% * 200 )
= 1 + 4 + 110
= 5.4 clock cycles
to get clock cycle per instruction, we need to divide 1000 memory references by 1 memory reference, which derives 1000 instructions. therefore, we need to multiply the miss by 1 to get the misses per 100 instructions. We have 40, 40 * 1 ie 40 L1 misses and 20 * 1 ie 20 L2 misses per 1000 instructions.