Consider 6 stage pipeline (S1 , S2, S3, S4, S5, S6) which allows all the instructions except branch instructions. Processor stops fetching the following instruction after the branch until the target address is available. Target address is available in the S4 stage. Program contain 40% of branch instructions. All the stages are balanced with a 2.3 GHz clock. MIPS rate of the processor is ________ (in 2 decimal places).