 # Average stall cycles per instruction cache

#1

Suppose that in 1000 memory references there are 150 misses in first level and 100 misses in second level cache. Assume that miss penalty from L2 cache to memory is 120 cycles. The hit time of L2 cache is 50 cycles.

If there are 4 memory references per instruction, the average stall per instruction is ?

#2

Stall cycles refer to the CPU cycles which degrade the performance of the processor. During stalling the CPU is actually not doing any productive work.

So for this question we would first calculate avg stall cycles per 1000 memory references.

Avg Stall Cycles/1000 memory references = (stall cycles if we don’t find the referred memory in L1 cache) + (stall cycles if we don’t find the referred memory in L2 cache)

= (miss rate L1* miss penalty L1) + (miss rate L2* miss penalty L2)

= (150/1000 * 50) + (100/1000 * 120)

=7.5 + 12

= 19.5

Avg Stall cycles per instruction is asked in the question.

So Avg stall cycles/instruction = (Avg stall cycles/1000memory references) * (4 memory references/Instruction)

= 19.5 * 4

=78

#3

Why miss rate of l2 is 100/1000? Shouldn’t it be 100/150?

And also I do not understand how the last formula was applied to get the answer…
U calculated AVG stall cycles per 1000 men refrences then how multiplying it by per instrn memory ref gave u the answer…(I am thinking in terms of unitary method)

#4

Good doubt. You are thinking to consider local miss rate of L2 instead of global miss rate. Read the question again. It specifies that out of 1000 memory references 150 misses in first level and 100 misses in second level which clearly signifies that you need to consider here global miss rate not the local one.
If in question it would have been specified that out of 150 misses in first level, 100 are misses in second level then you can definitely go for your proposed answer.