Architecturally question


Consider two cache organizations. First one is 32KB32KB 2−way2−way set associative with 32byte32byte block size, the second is of same size but direct mapped. The size of an address is 32bits32bits in both cases . A 2−to−12−to−1 multiplexer has latency of 0.6ns0.6ns while a k−bitk−bit comparator has latency of k/10ns k/10ns. The hit latency of the set associative organization is h1h1 while that of direct mapped is h2h2.

The value of h1h1 is:

  1. 2.4 ns2.4 ns
  2. 2.3 ns2.3 ns
  3. 1.8 ns1.8 ns
  4. 1.7 ns1.7 ns